1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to a bottom-source lateral diffusion metal oxide semiconductor field effect transistor (LDMOSFET) structure and manufacturing methods.
2. Description of the Prior Art
Conventional technologies to further reduce the source inductance for semiconductor power devices including the source inductance in FET, MOSFET and JFET devices are challenged by several technical difficulties and limitations. There are ever increasing demand to reduce the source inductance in the semiconductor power devices because more and more power devices are required to apply in the applications that demand high efficiency, high gain, and high frequency semiconductor power devices. The source inductance reduction can be achieved by eliminating the bond-wires in the package of a semiconductor power device. Many attempts are made to eliminate the bond-wires by configure the semiconductor substrate as a source connection for the semiconductor power devices. There are difficulties in such approaches due to the facts that typical vertical semiconductor power devices is arranged to place the drain electrode on the substrate. Referring to FIGS. 1A and 1B for the vertical power devices shown as trenched and planar DMOS devices respectively that use the substrate as the drain electrode with the current flows vertically from the source down to the drain region disposed at the bottom of the substrate. The top source electrode usually requires bond wires for electrical connections during a device packaging process thus increasing the source inductance.
Referring to FIG. 1C for a new vertical channel LDMOS device disclosed by Seung-Chul Lee et al, in Physica Cripta T101, pp. 58-60, 2002, with a structure shown as a standard vertical trenched DMOS wherein the drain contact is disposed on the side while the source is still on top of the active area. However, this device has a limitation due to a large cell pitch caused by the lateral spacing required by the top drain contact. In addition to the limitation of large cell pitch, the trenched FET device in general has a fabrication cost issue due to the fact that the trenched FET requires technologies that may not be available in all foundries and that tend to drive up the fabrication costs. For this reason, it is also desirable to implement the power device as lateral device with planar gate.
Several lateral DMOS with grounded substrate source have been disclosed. A lateral DMOS device typically includes a P+ sinker region (or alternate a trench) to connect the top source to the P+ substrate. The sinker region or the trench increases the pitch of the cell due to the dimensions occupied by the sinker or the trench. Referring to FIG. 1D for a device cross section disclosed by G. Cao et. al, in “Comparative Study of Drift Region Designs in RF LDMOSFETs”, IEEE Electron Devices, August 2004, pp 1296-1303. Ishiwaka O et al; disclose in “A 2.45 GHz power Ld-MOFSET with reduced source inductance by V-groove connections”, International Electron Devices Meeting. Technical Digest, Washington, D.C., USA, 1-4 Dec. 1985, pp. 166-169. In U.S. Pat. No. 6,372,557 by Leong (Apr. 16, 2002) attempts are made to use a buried layer at the interface of the P+ and P− epi layers to reduce the lateral diffusion and hence reduce pitch. In U.S. Pat. No. 5,821,144 (D'Anna and Hébert, Oct. 13, 1998) and U.S. Pat. No. 5,869,875, Hébert “Lateral Diffused MOS transistor with trench source contact” (issued on Feb. 9, 1999) devices are disclosed to reduce the cell pitch by placing the source sinker or trench on the OUTER periphery of the structure. However, in these disclosures, most of the devices as shown use the same metal over the source/body contact regions and gate shield regions and some of the devices use a second metal for drain and gate shield regions. These configurations generally form the P+ sinker through top down diffusion resulting in large cell pitch due to the significant lateral diffusions of the deep sinker diffusions used to connect the top source down to the highly doped substrate, that increases the overall size of the cell over the horizontal plane (cell pitch). A large cell pitch causes a large specific on-resistance which is a function of resistance and device areas. A large cell pitch also increases the device costs due to a larger size of the device and a larger size package.
Reducing the cell pitch of these prior art bottom-source devices results in shifts in the electrical performance of the device. For example, bringing the diffused sinker (which is p+ in doping) closer to the source side of the gate in FIG. 1D will result in a higher threshold voltage since the lateral diffusion of the diffused p+ sinker used to connect the top source to the bottom substrate will encroach in the channel region under the gate, which is also p-type, increase the doping concentration in the channel and hence, increase the threshold voltage, which is an undesirable result.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new device configurations and manufacturing method in forming the power devices such that the above discussed problems and limitations can be resolved.